A floating-point number is represented as a concatenation of a sign bit, an M-bit exponent field and an N-bit significand field. The IEEE standard for Binary Floating-Point Arithmetic (IEEE-754) defines formats for representing floating point numbers including single precision (M=8; N=24); double precision (M=11; N=53) and double-extended precision (M=15; N=64) formats.
Division of floating point numbers (a/b) is performed using reciprocal approximation by first obtaining a reciprocal approximation of 1/b and refining the reciprocal approximation by a series of subsequent multiplication and subtraction operations. In many processor architectures, ten bit reciprocal approximations of 1/b are pre-computed and stored in a lookup table having 265 entries that is indexed by the eight Most Significant Bits (MSBs) of the operand ‘b’ treated as a normalized real number in binary of the form 1.xx . . . x that is defined by IEEE-754 standard. The lookup table storing the 256 reciprocal approximations may be implemented in specialized logic as a Programmable Logic Array (PLA).
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.